1. Field of the Invention
The present invention pertains to the field of computer systems. More particularly, the present invention pertains to the field of prioritizing transfers of data between a bus agent and a memory circuit in a computer system.
2. Art Background
Decreasing memory access latencies in a computer system is one technique which generally improves overall system performance. Since computer systems often sequentially access consecutive memory locations, memory systems are frequently structured to provide lowest access times when such sequential access occurs. This may be accomplished, for example, by alternating between memory banks (one or more memory chips which reference a fixed amount of data such as a byte, word, or quadword) such that no bank is accessed two bus cycles in a row. Such bank switching affords each memory bank additional time to prepare for the next access cycle.
Additionally, improving overall locality of reference often increases memory access efficiency. Accesses to memory locations in close proximity are likely to remain within the same page or other similar memory structure. Additionally, accessing the same memory structure is often preferred because the memory interface is often optimized for accesses within that same memory structure. For example, in a paged memory system, accesses to the same page may allow a row address strobe (RAS) signal to remain active while the column address (CAS) is varied. Thus, efficiencies can result from both sequential and proximate (e.g., within the same page) memory accesses.
Separation of read and write accesses is another optimization which may advantageously reduce overall memory access times. Often, a bus agent such as a microprocessor posts write cycles to write buffers so long as no data conflict exists. Such reordering improves performance by deferring write access (if possible) until the bus is available. Grouping reads and writes may also reduce "turn around", the switching from reads to writes (or writes to reads) which is typically less efficient than repeating the same type of command.
One memory access protocol which provides several memory access commands is described in the Accelerated Graphics Port (A.G.P.) Interface Specification, Revision 1.0, Jul. 31, 1996, available from Intel Corporation of Santa Clara, Calif. This protocol defines a set of commands intended to provide a high bandwidth channel between a bus master (typically a graphics accelerator) and main memory. While the A.G.P. Specification provides command types, the implementation of memory controller arbitration and queuing logic are limited only by ordering rules and the latency targets chosen by the designer.
The A.G.P. Specification defines normal and high priority read and write commands of varying lengths. A set of commands of the same type may be referred to as a command stream. The high priority commands should be completed within the chosen maximum or guaranteed latency time, but each data stream need only be ordered with respect to itself. For example, high priority reads must remain in order only with respect to other high priority reads. Thus, within each priority, read data is returned to the bus master, and write data is written to memory in the order requested. Additionally, data transfers are "disconnected" from associated access requests, meaning that other A.G.P. request operations may separate an A.G.P. request and its associated data transfer. As is further described in the A.G.P. specification, a fence command, among other things, may be issued to guaranty the order of completion of normal priority commands if needed.
Thus, while the A.G.P. Specification facilitates high bandwidth communication between a bus master and memory by way of re-orderable multiple priority commands, it does not specify hardware structures or arbitration algorithms which may achieve specific latency goals. Available prior art memory access arbitration techniques do not adequately take advantage of sequential and proximate memory access techniques. Nor do prior art techniques provide an arbitration mechanism for re-orderable read and write commands which have multiple priorities.